Zigbee (XBee) + Arduino

Different SOC multiprotocol model 

Nordic Semiconductor is a company that specializes in ultra-low power performance wireless systems on a chip (SoC) and connectivity devices. It will produce several models of nRF SOC that can be used in our application, but we will choose just the most compatible and efficient SoC that ensures the good functioning of our system, so we will study and see the different specifications of some SoC, and here is the descriptive table of each model.

BT module

module	BT832F/BT832AF	BT832X	BT840F	BT840
SoC	nRF52832/810	nRF52832	nRF52840	nRF52840
BT range,1 Mbps, LMPI	760 meters	1140 meters	1000 meters	150 meters
BT range, 125 Kbps	---	---	2300 meters	320 meters
Peak current RX	5.4 mA	---	6.4 mA	6.4 mA
Peak current TX	7.5mA +4dBm	95mA +20dBm	13.6mA +8dBm	13.6mA +8dBm
Flash	512KB/192KB	512KB	1MB	1MB
RAM	64KB/24KB	64KB	256KB	256KB
GPIO pins	32	29	48	48
Price	$4.93/$3.79	$11.50	$7.78	$6.46

 From the previous table, we can say that our SOC must be the most BT range possible with the lowest price, so we chose the BT840E wireless modules that are characterized by power, flexibility and low power consumption, also it has all our needs and a better price compared to others. Using SOC Nordic nRF52840 is the solution of our problems since it is able to manage our system with all requirements.

😐The global nRF system

The nRF52840 is a powerful multiprotocol single chip solution for ULP wireless applications . It incorporates Nordic’s best inclass performance radio transceiver, an ARM Cortex M4F CPU and 512kB flash and 256kB RAM memory.

    👉Specifications

The nRF52840 SoC is part of the nRF52 Series that offers code-compatible devices across the series and simple software migration from the nRF51 Series.       😃 nRF52840 supports Bluetooth Low Energy, the ANT, 802.15.4, and user-proprietary 2.4 GHz protocols (high quality). An 802.15.4 protocol library and a certified USB stack are also available.

§     😃The 802.15.4 is a communication protocol defined by the IEEE. It is intended for wireless LAN networks of the LR WPAN (Low Rate Wireless Personal Area Network) family due to their low power consumption, their short-range and the low speed of devices using this protocol.

§    😃802.15.4 is used by many implementations based on proprietary protocols or IP (Internet Protocol), such as ZigBee and 6LoWPAN.

👉👉 Code development

Code development is easy, fast and safe, thanks to the clear between application code development and embedded protocol stacks that ensure compile, link and execution independence with the stack and associated debugging challenges.

The Bluetooth low energy and ANT stack is a pre-compiled binary, leaving application code to be compiled stand-alone. An asynchronous model is used by the embedded stack interface that is driven by the events to eliminate the need for RTOS frameworks.

Soft Devices are all Nordic protocol stacks dedicated to SoC nRF52 that are programmable software stacks from Nordic which ensures the flexibility of the developed applications.

The development tools are provided by Nordic Semiconductor with a full range of hardware and software (firmware development).

👉👉👉  Block diagram

we will study the different internal elements of nRF multi-Protocol and see the interconnections between them in order to understand its modes of operation and determine the necessary GPIOs that complete our needs.

👉👉👉👉Main components of SoC multi-Protocol

 In this paragraph, we will define the main functions of our SOC based on the modules and devices available in this IC, so we will divide the device descriptions into separate sections containing the information needed to understand the operating modes and ensure the proper use of this product.

☝CPU

 ARM Cortex M4 processor with floating-point unit (FPU) has a 32-bit instruction set (Thumb 2 technology) that implements a superset of 16 and 32-bit instructions to maximize code density and performance. Processors developed since the 1980s, with architecture relatively simpler than others processor families. ARM processors have become dominant in the field of embedded computing, especially mobile telephony and tablets [13].

👆Characteristics

  ARM processor is characterized by a simple RISC architecture and a pipeline structure. It is able to access memory with several methods and the most common is the load / store. The Cortex M4 processor incorporates several features, for example, multiple high-performance bus interfaces, a low-cost debug solution with the optional ability to implement breakpoints, code patches, watchpoints, tracing, and system profiling, also to support printf () style debugging and bridge to a Trace Port Analyzer (TPA). Arm also contains several devices and components boost their performance and reliability that we will define them later.

We can also mention the external interfaces of Cortex M4 such as multiple memory and device bus interfaces, ETM interface trace and debug port interface. ARM processor requires Software Interface Standard (CMSIS) hardware abstraction layer which is available for our M4 version.

☝Architecture (Block diagram)

 The following figure shows the Cortex M4 block diagram, which illustrates all the main internal modules and interfaces.

Cortex M4 block diagram

✌ CPU options and support module

The ARM Cortex-M4 processor has a number of CPU options and support modules        implemented on the device.

                      👇Optional integrated configurable debug

A hardware debugging solution can be implemented with ARM M4 processor to provide high CPU and memory system visibility using a 2-pin JTAG port or 2-pin Serial Wire Debug (SWD) port.

There are several units and peripherals built into the processor for proper system operation and monitoring, including Trace Macrocell instrumentation (ITM), data monitoring points and profiling unit, and a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling information through a single pin. Many low-cost MCUs can implement a complete trace of the instructions thanks to the optional Embedded Trace Macrocell (ETM) system. Debuggers can use comparators that are provided by the optional Flash Patch and Breakpoint Unit (FPB), and these comparators also provide remap functions with up to eight words in the program code.

                        👇Floating Point Unit

           Each processor has at least one calculation unit for performing certain operations such as addition, subtraction and multiplication, the other operations can be implemented in software, for example, and the difference between these processors is the ability to perform complex computations. With precision and without limitation the speed execution, so here comes the role and the importance of FPU which allows to calculate all complex operations. ARM has an FPU that supports multiple operations with a single precision, so it provides conversion between fixed-point and floating-point data formats, as well as floating-point constant instructions.

👌 FPU functional

FPU has the ability to see the register bank containing an extension registry file with 32 single precision registers, so we can have these as 64-bit dual word registers (D0-D15), 32-bit single- word registers (S0-S31) and a combination of these registers.

The FPU provides three modes of operation to accommodate a variety of applications:

•         Full-compliance mode
•          Flush-to-zero mode
•          Default NaN mode

The ARM has output pins that support the cumulative exception status flag that is set by the FPU into the FPSCR register, so ARM has a lazy stack to reduce exception latency as well to reserve the place for FP state without registration of this information.

                       👇Memory Protection Unit (MPU)

 One of the specifications that boost the performance of ARM such as security and well process management is that it has a memory protection unit (MPU), this unit is a full support use for protection, access authorization and the ascending region priority which is the most important such that the highest priority is 7, and 0 for the lowest. So, there is a control access register which has access authorization bits to the region (TEX, C, B, AP and XN) which generates an error during unauthorized memory access and all that to ensure good management of priority and decision.

In addition, each MPU_TYPE has a specific address corresponding to a region defines the MPU Type register (Control, alias, size ...).

                     👇 Nested Vectored Interrupt Controller (NVIC)

Our choice of ARM processor is confirmed by the low power consumption since ARM has the possibility to control the power management and the management of exceptions and interruptions, thanks to optional component in ARM called NVIC. This last maintains knowledge of the stacked, or nested, interrupts to enable tail-chaining of interrupts, it supports up to 240 interrupts each with up to 256 levels of priority.

In privileged mode, we can access the NVIC by keeping the Configuration Control Register deactivated to avoid interrupts and enter a state in the user mode.

NVIC registers are located within the SCS and are all little endian.

There are two types of interrupts associated with the ARM processor:

Level Interrupt: Used for FIFO and Buffer devices, and consists of being held until cleared by ISR accessing the device or by repeated calls.

A pulse interrupt can be reasserted during the ISR so that the interrupt can be in the pending state and active at the same time. These interrupts are mainly used for external signals and for rate or repeat signals. The operation undergoes time conditions such that the second pulse does not arrive before the first pulse is activated. The second entry in the pending state has no effect because it is already in this state. However, if the interruption is triggered for at least one cycle, the NVIC locks the pending bit. When ISR is enabled, the pending bit is cleared. If the interrupt reapplies while it is enabled, it can lock the pending bit again.

                                    👇ARM Debug Interface

This interface makes it possible to specify and manage the different accesses mapped in memory to the ARM or SoC devices constituting our complete system. The processor architecture defines registers that will be covered by this debug interface specification such as the target address, data transfer, status and port identification ...).

 The processor performs several tasks, it will process elements and transmits them to the PC via the JTAG, and during this process, components internal to the processor called macrocell collect information on the elements processed. There are several types such as Macrocel Information, Macrocell Trace, Macrocell Embedded trace, Macrocell Bus and so on.

☝☝Bus Architecture

 A system bus is characterized by debit and protocol. There are several compromises between the complexity of the bus and its performance. We find the same thing in a SoC.

👉      Bus interconnection

Time-sharing interconnection system connect the processor to the memory & peripherals (example: ISA bus).

👉        Buses designed for SoCs

 Several bus standards exist specifically for SOCs to avoid several external and internal constraints and to increase system speed since all transactions are done internally.     

Here are some of the most used standards

•         The AMBA standard (essentially around ARM processors)
•        IBM's Core Connect standard for PowerPCs
•         STBus standard, defined by ST Micro (use +/- internal)
•         Avalon standard used by Altera (SOPCBuilder)

👉       Characteristics

•         Complex protocols, with multiple masters
•          High performance-oriented bus ("burst" transfers)
•          Simplified protocol if performance is not a constraint.

Advanced Microcontroller Bus Architecture (AMBA) designed by ARM, and simplifies integration at the system level.

Advanced High-Performance Bus (AHB): bus fast, synchronous, multi_master system.

Advance System Bus (ASB): an alternative to the AHB system, used in cases where the high performance of the AHB bus is not required.

Advanced Peripheral Bus (APB): Peripheral bus, slower and lower power consumption (for slow devices), synchronous, single master.

To implement the AMBA protocol, ARM provides three bus interfaces such as 3 AHB-Lite Protocol, AMBA 3 APB for CoreSight and Debug Components, AMBA 3 APB Specification.

✌✌       Memory

Storing information meets three non-exclusive needs, retains information in a secure place to meet, a legal or conventional constraint (data archiving), make information available, reuse information (data processing).The method of storage is chosen according to several criteria such as the frequency of use of the information, the criticality of the information, the continuity of the information, the confidentiality of the information, the volume of information to be stored, the time allocated to the storage process and its cost. The watchword for storage techniques is: more capacity, faster, more reliable, and cheaper. This is why media types are varied and often evolve. There are several types of memory for storing codes and data so we can cite RAM and flash memory which are integrated in our nRF Multiprotocol.

👉        RAM

System memory or volatile memory (Random Access Memory): the computer memory in which a computer places the data during their processing, they characterize by:

·         Its timeliness of access (essential to provide data to the processor quickly)

·         Its volatility (this volatility implies that data is lost as soon as the computer stops being powered by electricity).

There are 9 AHB RAM slaves that are connected to 2 * 4 kB of RAM sections, except RAM AHB slave 8 which is connected to 6 * 32 kB. The RAM contains a configuration register which ensures the power control of each section of the RAM to minimize energy consumption and optimize energy efficiency.

👉       Flash memory

Flash memory is a re-recordable semiconductor mass memory, that is to say a memory with the characteristics of a RAM but whose data does not disappear during a power down. Thus, the flash memory stores the data bits in memory cells, but the data is stored in memory when the power supply is cut. Its high speed, service life and low power consumption (which is even zero at rest) make it very useful for many applications. There are two buses (ICODE and DCODE) that connect the flash memory to the CPU and provide access to each 256 * 4 KB pages.

        Our system does not require external memory since there is 1 MB of flash memory and 256 KB of RAM in the nRF52 (sufficient space for code and data storage).

Memory map

The CPU and the Peripherals having EasyDMA can access memory via the AHB Multilayer Interconnect.

☝☝☝AHB Multilayer

To ensure a high speed of communication between the different Soc devices, the designers offer a well-structured architecture that allows parallel access between several masters and slaves of the system using AHB Multilayer. Each master bus is connected to the slave equipment using an interconnection matrix, and when two or more bus masters request access to the same slave device, a priority algorithm is applied to resolve access therefore:

·         Access to slave equipment is given to the master with the highest priority compared to another requesters access.

·         Bus masters with lower priority are stalled until the higher priority master has completed its transaction.

·          If the higher priority master pauses at any point during its transaction, the lower priority master in queue is temporarily granted access to the slave device until the higher priority master resumes its activity.

·         Access is forbidden at the same time, so bus masters that have the same priority are mutually exclusive.

✌✌✌EasyDMA

EasyDMA is an easy-to-use direct memory access module, and it is an AHB bus master similar to the CPU and it is connected to the AHB multilayer interconnect for direct access to the Data RAM. Flash access is not possible with the EasyDMA.     

A peripheral can implement multiple EasyDMA instances as mentioned in figure 2.3.

EasyDMA

☝✌Non-Volatile Memory Controller (NVMC)

The number of flash memory read by the CPU is unlimited while writing and deleting is limited and well determined as well as how it can be written. The non-volatile memory controller (NVMC) is used for writing and erasing the internal flash memory and the UICR (user information configuration registers, non-volatile memory registers for configuring user-specific settings).

In summary, here is a memory layout that defines the different devices and the connection between them, this architecture is well structured based on mapping the same physical RAM to both the Data RAM region and the Code RAM region, also the existence of an application to partition the RAM in those regions so that one does not corrupt the other.

Memory layout

☝☝✌Power management unit (PMU)

Power management automatically detects power and clock resources and selects operating modes of power controllers to minimize power consumption, so there are LDO and DC / DC controllers that optimize the energy efficiency of the system.

The system can be powered by one of two voltage modes, normal mode or high voltage mode.

·         Normal mode: When the supply voltage is connected to the VDD pins, this mode is activated (1.7 v to 3.6 v).

·         High mode: When the supply voltage is connected to the VDDH pins, this mode is activated. (2.5 v to 5.5 v)

Only one pin must be connected by the supply voltage, that is why there is a register MAIN REGSTATUS allows to read the current mode of supply.

We can power the system via the USB device, but this is not the case in our application because we use a battery as power source (external power) and the USB device exists except for UART communication. So according to the datasheet we will choose the circuit configuration V.6 which consists in feeding the two pins VDD and VDDH in common with a stabilized power supply (battery) comes from an external regulator.

✌☝Peripheral interface

There are event registers and interrupts that can be configured for a given event used to indicate peripheral events to the CPU that is the controller of these devices by writing in configuration registers and task registries.

Ø  Peripheral ID

The base address is directly connected with the peripheral ID which is associated with a block of 0x1000 bytes of address space that means 1024 32-bit registers.

Connection between base address and peripheral ID

 Peripherals may share the same ID, which may impose one or more of limitations

• Sharing registers or other common resources.
•  Limitation when using devices (Only one device).
• A specific schema must be followed when switching from one device to another (Disable first and activate the second device).

😃 Peripherals with shared ID

In general, simultaneous use of peripherals sharing an ID and a base address is prohibited, so one device can be used at a time. we can note the exception of ID 0.

😃 Peripheral registers

This is about enabling devices to perform certain tasks and events, so there is a configuration of device registers.

😃Bit set and clear

There is a "set-and-clear" model that tracks the main register through a dedicated SET and CLR register. The SET is used to define individual bits in the main register, while the CLR register is used to clear individual bits in the main register.

Reading the SET or CLR registers returns the value of the main register.

SET=1: register will set            |       SET=0: register has no effect

CLR=1: register will clear         |       CLR=0: register has no effect

We will explain four different types of actions that are tasks, events, shortcuts, and interrupts.

v 👉 Tasks

Triggering actions on a device requires the presence of tasks, so a device can implement one or more tasks with each task having a separate register in the group of registers. The triggering of a task can be done when:

•          Firmware writes 1 to the task register
•          The peripheral itself or another peripheral toggles the corresponding task signal.

v  👉Events

While events are used to inform devices and the CPU of events that have occurred, and like tasks, each event with a separate registry in the event register group of a sui device can generate more events. When the device itself switches the corresponding event signal and the event register is updated, then the event is generated.

An event register is only cleared when firmware writes 0 to it. Events can be generated by the peripheral even when the event register is set to 1.

v  👉Shortcuts

A direct connection between an event and a task in the same device is called shortcut. When an event associated with a shortcut is generated then its associated task is automatically triggered.

v 👉Interrupts

Interrupts are supported in all devices, and events are responsible for generating interrupts that are distributed so that each device occupies only one event and the device ID.

v  👉Interrupt clearing

Entering "0" in an event register or disabling an interrupt using the INTENCLR register cancels an interrupt, and according to the manufacturer, up to four clock cycles can be the CPU, so this delay can cause the reoccur of an interruption even if a new event has not happened. In fact, the program leaves an interrupt manager after the interruption has been erased or deactivated, but before four clock cycles have elapsed. So, to avoid this problem the program must read from one of the device registers, for example, the INTENCLR register used to disable the interrupt.

This will cause a delay of less than four cycles and will ensure that the interrupt is cleared before exiting the interrupt handler.

The relationship between tasks, events, shortcuts, and interrupts

✌☝☝Debug IN

Flexibility and power are one of the basic features that must be found in every system, so the designers take in consideration debugging and monitoring the system to ensure control and smooth operation. In our case, the nRF52 module has a debug and trace block connected with the ARM processor, the following figure shows the latter.

 Debug and trace block diagram

There is a protocol called Serial Wire Debug (SWD) implied by the debug port (SW-DP), this protocol is a two-pin SWDCLK and SWDIO serial interface, and as shown in the figure above, all of these form the DAP that provides access to the devices after passing through the Control Access Port (CTRL-AP), thus the default access port in the CPU (AHB-AP).

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