Microprocessor characteristics & Architecture Classifications

    

Microprocessor characteristics 

& 

Architecture Classifications

A microprocessor is a processor whose all components have been sufficiently miniaturized to be grouped in a single box. Functionally, the processor is the part of a computer that executes instructions and processes program data.

The integrated circuit (IC), also called electronic chip, is an electronic component, based on a semiconductor, reproducing one or more electronic function (s) more or less complex (s), often integrating several types basic electronic components in a small volume (on a small plate), making the circuit easy to implement.

There is a very wide variety of these components divided into two broad categories: analog and digital.

A computer program is a set of operations intended to be executed by a computer.

A source program is a code written by a computer scientist in a programming language. It can be compiled into a binary form or directly interpreted.

A binary program describes the instructions to be executed by a microprocessor in digital form. These instructions define a machine language.

A program is usually part of a software package: a set of digital components intended to provide an IT service; software may have multiple programs. It is found in computer devices (computer, game console, ATM machine ...), in computer equipment parts, as well as in many electronic devices (printer, modem, GPS, mobile phone, washing machine, appliance digital photo, digital TV decoder, electronic injection, autopilot ...).

Computer programs are concerned by copyright and are subject to legislation close to artistic works.

Microprocessor characteristic

Microprocessor possesses a combination of characteristics which determine their power expressed in millions of instructions per second (MIPS), these characteristics are distributed according to several terms, we can distinguish the physical characteristics such as connection type, the shape, internal cache capacity etc., and the electrical characteristics that define the power consumption and operating speed expressed in megahertz. These last characteristics are insufficient to determine processor efficiency and performance, it is necessary to determine the logical characteristics by defining the architecture (RISC or CISC) and thus the set of instructions and the frequency.

        Performance of a processor

Two parameters can be used to measure the processor performance:

·         The response time or execution time of a certain task: time elapsed between the start and the end of the task.

·         Throughput: the total amount of work done in a certain time.

Improving the response time always implies an improvement in the throughput. However, the opposite is not always true: an increase in the number of processors of a computer increases throughput, without necessarily improving response time.

We will consider the execution time as a parameter principal for calculating the performance of a processor.

The execution time depends on three factors:

·         The number of machine instructions executed.

·         The average number of clock cycles per machine instruction.

·         The clock periods.

There are two types of processors, depending on the optimized setting:

·         CISC processors (Complex Instruction Set Computer).

·         RISC processors (Reduced Instruction Set Computer).

Time = 1 / performance =

(number of instructions) x (number of cycles per instruction) x (clock period)

Performance Measure: SPEC2000:

To solve the problem of choosing a test programs (benchmarks) to be used to measure performance, several manufacturers have teamed up to create SPEC (Standard Performance Evaluation Corporation).

There are two main groups of benchmarks, one for numbers integers and the other for real numbers. A value of performance is calculated for each of these groups, called SPECint and SPECfp. Only one value is given for each group: the geometric mean.

👉  SPEC CPUint2000: 12 programs written in C and C ++.

👉 SPEC CPUfp2000: 14 programs written in Fortran and C.

Architecture Classifications

External processor architecture is the processor model seen from the outside. This is the interface between the hardware and the software. So, we need to know the functional specification of a processor, from the point of view programmer in machine language. The architecture includes instruction set data, set of registers visible by the programmer, a memory organization, input-output and modalities of possible multiprocessor support.

Currently, there are several architectures that include registers, memory, and I / O all manipulated by the machine instructions of the programs, so there is the set statement that defines the way or behavior of each machine statement. We can dedicate several architectures.

CISC architecture

A CISC architecture offers many addressing modes, some of which are often complex. The instruction set often has many complex instructions that will be realized in several cycles.

RISC architecture

 RISC architecture offers a relatively small set of instructions. Each of these instructions is supposed to be executed in one cycle. Addressing modes are simpler than in a CISC architecture. The architecture generally offers a large number of general registers. These characteristics favor the optimal use of the pipeline at the microarchitecture level.

RISV-V extends the open-source movement into CPU ISA. It is an open-source ISA that is license-free and royalty-free. As RISC-V is void of any licensing, the ISA can be used for building custom processors with zero licensing cost. It is gradually building an ecosystem. In Embedded World 2017, RISC-V showcased the extensive ecosystem with FPGA solutions, security IPs, debug infrastructure, etc.

Few ARM customers have already started using RISC-V for designing custom processors. Now, SoC design companies can develop custom processors at a low cost, without the paying licensing rents. With some NRE investment, these firms can develop the SoC and get it manufactured in fabs. Thus, the price of the processor will be lesser than those based on ARM IPs. At the face value, it looks like we have found an ideal candidate that has the potential to become the dominant ISA for IoT industry. With customization and zero licensing cost, RISC-V looks like a winner.

We have several inconvenient of open RISC_V based design

 Differences between software and hardware

·         Software only requires time and effort to be developed.

·         The material involves concrete components, for which someone has to pay.

·         The software rework as many times as desired after performing tests on the hardware, the emulator, etc.

·         Bugs can be fixed with an investment of time and effort, possibly with a minimal cost. However, bugs in hardware can be a loss of a million dollars! Several laps of a processor can cost a lot.

·         Hardware design is more complex than software development.

·         Requires a vast IP and EDA ecosystem around the IP of the procreator (because in a SOC the IP of the processor is only a part, so need other physical and peripheral IP).

·         Necessary to license on rentsWith ARM ISA, most of the issues mentioned above are fixed. We can access proven IP addresses, a robust ecosystem (software, cloud services, security solutions, silicon vendors, manufacturing plants) and dedicated support instead of the community support offered by ISA Open Source. The complexity of the design is reduced.

  Superscalar processor

 During each cycle, the superscalar processor instruction (hardware) transmission logic examines the instructions in a sequential program to identify those that can be issued during this cycle. The program is compiled in the same way as on a sequential processor without ILP.

    VLIW processor

 VLIW processors exploit parallelism by relying on the compiler to determine which instructions can be executed in parallel.

The Very Long Instruction Word (VLIW) is a long statement consisting of several basic instructions. The use of this VLIW thus makes it possible to execute several instructions in parallel on different functional units (UF).

So, here is the table that summarizes the main architectures

Classification of architecture

  Instruction sets

        The choice of processor ensures the proper functioning of our systems such as speed and flexibility so our goals are

• Reduce memory access
• Increase simultaneous memory access
• Reduce the time spent doing calculations

Indeed, architects have turned to parallelism that allows them to improve performance by performing several tasks simultaneously. So, exploitation of parallelism is divided into four categories:

• SIMD Architectures
• MIMD Architectures exploiting the parallelism of instructions
• ILP (Level Parallelism Instruction)
• Architectures multi-cores

Towards more parallelism

• SISD = Single Instruction, Single Data
• SIMD = Single Instruction, Multiple Data
• MIMD = Multiple Instruction, Multiple Data

        SIMD

It is introduced on general-purpose processors and efficient processors for parallel algorithms, there are two types of SIMD:

👉  Parallel units able to perform the same operation on different data, example: ADSP-2116x.

👉  Sharing the processing unit (example: Pentium MMX instructions)

• Share a data word in subwords

• Performs sub-word calculations

An SWP (Sub Word Parallelism) operator calculates in parallel the LSB and MSB portions of the input data. (examples: Lucent DSP16xxx, ADI ADSP-2116x...).

More details:

👉 http://ftp.cvut.cz/kernel/people/geoff/cell/ps3-linux docs/CellProgrammingTutorial/BasicsOfSIMDProgramming.html

MIMD approach (ILP)

ILP processors exploit the fact that many of instructions in a sequential program do not depend on those that precede them in the program. The ILP approach consists in providing the µ_processor with several execution units working in parallel. The instructions are then distributed among the different execution units.

        Limits of ILP

The performance of ILP processors is limited by the amount of parallelism of instructions to locate in the program. It is limited by data dependencies and connections.

Example of the parallelism of instructions: ILP processor with 2 execution units

LD r1, (r2)

ADD r5, r6, r7

SUB r8, r1, r4

MUL r8, r9, r10

ST (r11), r4

         Addressing modes

Addressing modes are an aspect of processor architectures and their instruction sets. It defined how machine language instructions identify their operands. An addressing mode specifies how the effective memory address of an operand is calculated from values contained in registers and constants contained in the instruction or elsewhere in the machine. There are several types of addressing depending on the type of use, we can recognize the addressing mode for the connection, for data and for numerical calculations (DSP).

       Comparison between processors 

This paragraph provides an interesting comparison between the most popular and widely used Reduced Instruction Set Architecture (RISC) processors, which will help to determine which ISA of these selected processors best suits our needs and to ensure the right choices according to the requirements.

Classification of processors